Many high speed serial communication systems only transmit data over the communication media. In other words, these systems do not transmit clock signals that may be used by a receiver to recover the data. Consequently, receivers for high speed serial communication systems typically include clock and data recovery circuits that produce a clock signal synchronized with the incoming data that is then used to recover the data. Data is typically recovered by generating a clock signal at a frequency that matches the frequency of an incoming data stream. The clock is then used to sample or recover the individual data bits.
For example, FIG. 1 illustrates a typical receiver that utilizes a clock and data recovery circuit 10 and retimer 20 to generate recovered data 30. Typically incoming data 40 is amplified by one or more buffer stages 50 and the clock and data recovery circuit 10 generates an extracted clock signal 70 that has a phase and/or frequency that is fixed relative to the phase and/or frequency of the incoming amplified data 80.
The clock and data recovery circuit 10 may comprise a phase lock loop or delay lock loop that aligns the edges of the extracted clock, for example the rising edge, with the transition edge of the incoming data. In this instance the falling edge of the clock is approximately in the middle of the incoming data symbol. In this instance the retimer 20 may comprise, by way of example, a falling edge flip-flop that is triggered to recover the transmitted data on the falling edge of the clock.
In operation however, bandwidth limitations inherent in many communication media tend to create increasing levels of data distortion with increasing data rate and channel length. For example, band-limited channels tend to spread transmitted pulses. If the width of the spread pulse exceeds a symbol duration, overlap with neighboring pulses may occur, degrading the performance of the receiver. Therefore, typical high speed receivers may also include an adaptive equalizer, such as, for example, a decision feedback equalizer that cancels or reduces inter-symbol interference caused by micro-reflections in the channel.
For example, FIG. 2 is a simplified block diagram of a conventional one tap decision feedback equalizer 200 where a summer 210 combines the incoming data 220 with a feedback signal 230. A slicer 240 converts the output of the summer (soft decision) to a binary signal. A flip-flop 250 recovers the data from the binary signal in response to a clock 260. A multiplier 270 scales the recovered data by an equalization coefficient (g1) to generate the feedback signal 230 (typically a negative number) that is then combined with incoming data. The equalizer therefore serves to subtract a previous symbol from a current symbol to reduce or eliminate channel induced distortion such as inter-symbol interference.
In conventional receivers the extracted clock from the clock and data recovery circuit drives the flip-flop to recover equalized data. For example, FIG. 3 is a simplified block diagram of a decision feedback equalizer and clock and data recovery circuit based receiver 300. In this receiver incoming data is again amplified by one or more buffer stages 310. The clock and data recovery circuit 320 generates an extracted clock 330 from the amplified data (D1) and drives the decision feedback equalizer flip-flop 340 that recovers the equalized (D2) data provided by slicer 350.
In the illustrated receiver the clock and data recovery circuit 320 aligns the rising edge of the extracted clock 330 with the transition edge of the amplified data D1. In practice, however, the rising edge of the extracted clock 330 should be aligned with the equalized data (D2) output by the slicer 350 for proper data recovery by flip-flop 340. Therefore, the time delay through summer 360 and slicer 350 should be equal to the time delay through buffer stage(s) 310 to ensure that the input data (D2) and clock signal 330 of flip-flop 340 are aligned to properly recover the equalizer data.
Accordingly, conventional receivers typically include delay matching stages (not shown) to adjust the delay through the buffer stage(s) 310 to match the delay through summer 360 and slicer 350 to align the binary signal (D2) and extracted clock signal 330. In practice, however, process variations and performance variations over temperature may make it difficult to match the delay through the buffer stage(s) with the delay through the summer and slicer, thereby limiting the performance of conventional receivers.
Further, when inter-symbol interference is relatively large the clock and data recovery circuit may no longer properly track the transition edges of the incoming data. In these instances the extracted clock signal 330 is no longer locked to or synchronized with the incoming data stream and the recovered equalized data may be corrupted. Therefore conventional receivers often have limited tolerance to inter-symbol interference.